Why participate?

The seminar focuses on Boundary Scan/JTAG testing and in-system-programming for R&D, engineering- and production.

Novices and interested electronic engineers will meet colleagues, already using Boundary Scan and will appreciate the information on:
IEEE and related standards
Emulation testing and programming
Integrated, modular software and hardware solutions
Quo Vadis: what will bring the future.

Existing Göpel users will be updated on the latest additions and evolution in the System Cascon software workbench.

When and Where?

Thursday October 20th in the Hotel Steensel, Steensel.
Please register yourself and your colleagues with the registration link.

A confirmation and route description will be sent one week in advance.
The seminar takes one day from 09:30h till 16:00h. Coffee will be ready for you from 9.00. The seminar is free of charge.

Agenda

Göpel Cascon Software overview:
The test and programming capabilities as well as the latest features of the Cascon software will be discussed through presentations and practical demonstrations.

Göpel Boundary Scan Hardware & Integration:
Powerful and flexible hardware solutions are available for standalone use and integration of JTAG/Boundary Scan in ICT, functional and flying probe testers. Different standalone test-setups using Göpel Scanflex and Scanbooster hardware will be demonstrated.

VarioTAP: Test and programming via emulation:
Testing high frequency digital boards with fast I/O interfaces or Fast on-chip and on-board Flash programming requires a dynamic emulation approach.
VarioTAP is a technique that allows the seamless and
simultaneous use of both emulation and Boundary Scan .

ChipVORX: FPGA embedded instrumentation
Benefit from onboard FPGA resources! ChipVORX is a new in-system technology for the configuration and control of chip embedded test, debug, and programming functions fully synchronized with Boundary Scan operations.